1. Field of the Invention
The present invention relates to information handling systems and more particularly to enhancements to processor microcode load mechanisms for information handling systems.
2. Description of the Related Art
As the value and use of information continues to increase, individuals and businesses seek additional ways to process and store information. One option available to users is information handling systems. An information handling system generally processes, compiles, stores, and/or communicates information or data for business, personal, or other purposes thereby allowing users to take advantage of the value of the information. Because technology and information handling needs and requirements vary between different users or applications, information handling systems may also vary regarding what information is handled, how the information is handled, how much information is processed, stored, or communicated, and how quickly and efficiently the information may be processed, stored, or communicated. The variations in information handling systems allow for information handling systems to be general or configured for a specific user or specific use such as financial transaction processing, airline reservations, enterprise data storage, or global communications. In addition, information handling systems may include a variety of hardware and software components that may be configured to process, store, and communicate information and may include one or more computer systems, data storage systems, and networking systems.
It is known to provide information handling systems with processors which include a plurality of processor cores. In certain known processor architectures, on each power-up, the basic input output system (BIOS) of the information handling system can be required to load processor microcode, separately to each core, before multi-level caches can be enabled. To load microcode patches (such as during a power on self test (POST) operation), the BIOS wakes up each non-boot strap processor (BSP) core (i.e., all of the cores of the processor other than the boot processor core) and then loads microcode and then enable cache on each of the application processor cores (i.e., the non-BSP cores). As the number of cores in each socket increases, this process increases the amount of resume time required to perform power on self test.
In certain multicore processor architectures, the overhead, especially during an S3 state resume process, for microcode load or multiprocessor initialization, can be due to all the bus cycles from all of the application processors (APs) to fetch the code and data, and looping around semaphores for synchronizing amongst various application processors.
It is known to provide processors with identical cores in each of the processor sockets. Additionally, the number of cores continues to increase (e.g., known processors can include four cores, but this number is quickly increasing to eight, and potentially more thereafter). With identical cores, each of the plurality of cores require substantially the same microcode. Thus, an increase in the number of cores within an information handling system presents a corresponding increase in the amount of time required to wake up each of the cores and load microcode to the core.
Accordingly, it is desirable to provide an information handling system with a more efficient mechanism for loading microcode to a plurality of identical cores.